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- Dr. Marcus Bronzel
- Gordon Cichon
- Hendrik Seidel
- Pablo Robelly
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- Transition from CISC to RISC for DSPs
- STA: Synchronous Transfer Architecture
- Means: All data transfers between modules take place synchronously
- Good for Compiler as well as for Signal Processing
- Requirement: Separate State and Behavior
- Put behavior, i.e., computation, in functional units (FU)
- Put state into register files and memories
- Benefit:
- Quickly model arbitrary processors bottom-up with your know-how and IP
about functional units
- Save work at tedious development of simulators, instruction controllers,
memories and register files.
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- Mouse gencore generates the following from a Machine Description:
- Documentation:
- Report on ISA layout
- Lisa:
- Complete LISA model supporting SIMD and VLIW
- LISA behaviors
- Convenient VLIW Assembly Preprocessor
- Lisa generates:
- Assembler and Linker
- Machine Simulator w/ Debugger
- VHDL:
- VHDL package w/ constants
- Core toplevel w/ interconnection wires and MUXes
- SIMD slices w/ interconnection wires and MUXes
- Instruction Decoder
- Register files w/ debug capability
- Memories using Altera Mega-Functions w/ debug capability
- Synthesis scripts for Synopsys and Altera
- Unified debug interface for in-circuit debugging
- Stubs for FU implementation
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- Improved core generator: now creates VHDL, System-C, and LisaTM
- Web-interface for evaluation purposes
- MOUSE-gencore is an efficient part of the toolchain
- Allows quick integration of functional units into a DSP
- The MOUSE integrated design flow is more effective than the traditional
design flow
- In use for M5
- Also used for 802.11/UMTS combi chip
- Reuse: Expertise gained in one project can be leveraged to other
projects
- An additional boost in productivity is expected by extending the Mouse
toolset
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- Thank you for your attention
- Please visit us online at:
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