1	Mouse Core Generator Demo Gordon Cichon Hendrik Seidel Pablo Robelly
2	Integrated Design Flow for Signal Processing Applications
3	Integrated Design Flow of Mouse
4	Design Principles of STA Transition from CISC to RISC for DSPs STA: Synchronous Transfer Architecture Means: All data transfers between modules take place synchronously Good for Compiler as well as for Signal Processing Requirement: Separate State and Behavior Put behavior, i.e., computation, in functional units (FU) Put state into register files and memories Benefit: Quickly model arbitrary processors bottom-up with your know-how and IP about functional units Save work at tedious development of simulators, instruction controllers, memories and register files.
5	STA – Architectural Template
6	Mouse gencore delivers: Mouse gencore generates the following from a Machine Description: Documentation: Report on ISA layout Lisa: Complete LISA model supporting SIMD and VLIW LISA behaviors Convenient VLIW Assembly Preprocessor Lisa generates: Assembler and Linker Machine Simulator w/ Debugger VHDL: VHDL package w/ constants Core toplevel w/ interconnection wires and MUXes SIMD slices w/ interconnection wires and MUXes Instruction Decoder Register files w/ debug capability Memories using Altera Mega-Functions w/ debug capability Synthesis scripts for Synopsys and Altera Unified debug interface for in-circuit debugging Stubs for FU implementation
7	Demonstration Roadmap
8	Example Processor Architecture
9	MD-Builder
10	Generated LISA Cycle Accurate Instruction Set Simulator
11	VHDL-Simulation and Synthesis
12	Unified In-Circuit Core-Debugging