SAMIRA: Silicon Implementation
						§ 17 FPUs: ~3.5 GFLOPS peak § Synthesis: Synopsys DesignCompiler § Place&Route: Cadence Encounter § Target Technology: UMC 0.13µm, 9-layer-metal process @ 1.2 V (1 gate = 5.1 µm2) § Total Area: ~10 mm2 mem: ~7.5 mm2, core: ~2.5 mm2 § ηArea = 41.36% § Power Consumption: 360 mW @ 210 MHz (simulated) § Tape-out: November 2004 § Silicon expected: June 2005